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71M6521DE/DH/FE Data Sheet
In counter mode, the register is incremented when the falling edge is observed at the corresponding input signal T0
or T1 (T0 and T1 are the timer gating inputs derived from certain DIO pins, see the DIO Ports chapter). Since it takes
2 machine cycles to recognize a 1-to-0 event, the maximum input count rate is 1/2 of the oscillator frequency. There
are no restrictions on the duty cycle, however to ensure proper recognition of 0 or 1 state, an input should be stable
for at least 1 machine cycle.
The timers/counters are controlled by the TCON Register
Timer/Counter Control Register ( TCON )
MSB
LSB
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Table 19: The TCON Register
Bit
TCON.7
TCON.6
TCON.5
TCON.4
TCON.3
TCON.2
TCON.1
TCON.0
Page: 26 of 107
Symbol
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Function
The Timer 1 overflow flag is set by hardware when Timer 1 overflows. This flag
can be cleared by software and is automatically cleared when an interrupt is
processed.
Timer 1 Run control bit. If cleared, Timer 1 stops.
Timer 0 overflow flag set by hardware when Timer 0 overflows. This flag can be
cleared by software and is automatically cleared when an interrupt is
processed.
Timer 0 Run control bit. If cleared, Timer 0 stops.
Interrupt 1 edge flag is set by hardware when the falling edge on external pin
int1 is observed. Cleared when an interrupt is processed.
Interrupt 1 type control bit. Selects either the falling edge or low level on input
pin to cause an interrupt.
Interrupt 0 edge flag is set by hardware when the falling edge on external pin
int0 is observed. Cleared when an interrupt is processed.
Interrupt 0 type control bit. Selects either the falling edge or low level on input
pin to cause interrupt.
Table 20: The TCON Register Bit Functions
Rev 3
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